Reference is now made to FIG. 1 showing the general configuration of a conventional metal oxide semiconductor (MOS) field effect transistor (FET) 10 device. A substrate 12 supports the transistor. In this example, the substrate is of the silicon-on-insulator substrate 12 type which includes a substrate layer 14, a buried oxide (BOX) layer 16 and a semiconductor layer 18. An active region 20 for the transistor device is delimited by a peripherally surrounding shallow trench isolation 22 that penetrates through the layer 18. Within the active region 20, the layer 18 is divided into a channel region 30 which has been doped with a first conductivity type dopant, a source region 32 (adjacent the channel region 30 on one side) which has been doped with a second conductivity type dopant, and a drain region 34 (adjacent the channel region 30 on an opposite side from the source region 32) which has also been doped with the second conductivity type dopant. Where the MOSFET 10 device is of the p-channel type, the first conductivity type dopant is p-type and the second conductivity type is n-type. Conversely, where the MOSFET device is of the n-channel type, the first conductivity type dopant is n-type and the second conductivity type is p-type. A gate stack 36 is provided above the channel region 30. This gate stack 36 typically comprises a gate dielectric 38, a gate electrode 40 (for example, of metal and/or polysilicon material) and sidewall spacers 42 made of an insulating material such as silicon nitride (SiN) deposited on the sides of the gate dielectric 38 and gate electrode 40. An interlevel dielectric (ILD) or pre-metallization dielectric (PMD) layer 46 is provided above the substrate and the gate stack. A top surface 48 of the layer 46 is processed with a chemical-mechanical polishing (CMP) process to define a planar surface. A set of metal contacts 50, typically formed of tungsten, extend from the top surface 48 through the ILD/PMD layer 46 in metal-filled contact openings to make electrical contact with the source region 32, drain region 34 and gate electrode 40. A first metallization layer M1 is then provided above the ILD/PMD layer 46, with the first metallization layer M1 comprising metal lines 54 formed in metal-filled via and/or trench openings in contact with the contacts 50 and surrounded by a planarized dielectric material layer 56.
As feature sizes in integrated circuit devices continue to shrink and operational speed increases, there is a need to make a thicker ILD/PMD layer 46 so as to reduce capacitance between the first metallization layer M1 and the active region 20 as well as between the first metallization layer M1 and the gate electrode 40. The thicker ILD/PMD layer 46 and reduced feature size accordingly necessitates the use of high aspect ratio metal contacts 50 (i.e., contacts made in openings with a height/width ratio >>1, for example, ≥4). It is a challenge to provide such high aspect ratio contacts without incurring problems associated with open yield and increased contact resistance. There is accordingly a need in the art for an improved contact configuration for interconnecting the first metallization layer M1 to both the active region 20 and the gate electrode 40.
In addition, improved structures for the metal lines and metal vias in the metallization layers of integrated circuits are needed to ensure device reliability and improve signal performance through resistance adjustment.